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CY2V9950
2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer
Features
* * * * * * * * * * * * * * 2.5V or 3.3V operation Split output bank power supplies Output frequency range: 6 MHz to 200 MHz Output-output skew < 150 ps Cycle-cycle jitter < 100 ps Selectable positive or negative edge synchronization Selectable phase-locked loop (PLL) frequency range 8 LVTTL outputs driving 50 terminated lines LVCMOS/LVTTL Over-voltage tolerant reference input 2x, 4x multiply and (1/2)x, (1/4)x divide ratios Spread-Spectrum-compatible Pin-compatible with IDT5V9950 and IDT5T9950 Industrial temperature range: -40C to +85C 32-pin TQFP package
Functional Description
The CY2V9950 is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features functions necessary to optimize the timing of high performance computer and communication systems. The user can program the output banks through 3F[0:1] and 4F[0:1]pins. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the PE pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock.
Block Diagram
Pin Configuration
TEST
PE
FS VDDQ 1
VSS
TEST
VDD
REF
2F1
3F0
R EF
3
3
PLL
FB
32 31 30 29 28 27 26 25 3F1
1Q 0
4F0 4F1 PE VDDQ4 4Q1 4Q0 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VDDQ3 3Q1 VSS VDD 3Q0 2Q1 2Q0 FB
FS
2F0 24 23 22 1F1 1F0 sOE# VDDQ1 1Q0 1Q1 VSS VSS 21 20 19 18 17
1F1:0 1Q 1
CY2V9950
2Q 0 2F1:0 2Q 1
3F1:0
3 3 /K
3Q 0 3Q 1 VDDQ 3
4F1:0
3 3 /M
4Q 0 4Q 1
VDDQ 4 sO E#
Cypress Semiconductor Corporation Document #: 38-07436 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised August 11, 2004
CY2V9950
Pin Definitions
Pin 29 13 27 22 Name REF FB TEST sOE# I, PD I/O[1] Type I LVTTL/LVCMOS I LVTTL 3-Level I 2-Level Description Reference Clock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW / HIGH the outputs are synchronized with the negative/positive edge of the reference clock. Please see Table 5. Select frequency of the outputs. Please see Tables 1 and 2. Selects VCO operating frequency range. Please see Table 4. Four banks of two outputs. Please see Tables 1 and 2 for frequency settings. Power supply for Bank 1 and Bank 2 output buffers. Please see Table 6 for supply level constraints Power supply for Bank 3 output buffers. Please see Table 6 for supply level constraints Power supply for Bank 4 output buffers. Please see Table 6 for supply level constraints Power supply for internal circuitry. Please see Table 6 for supply level constraints Ground. The divider settings, output frequencies, and possible configurations of connecting FB to ANY output are summarized in Table 3. Table 3. Output Frequency Settings Configuration FB to 1Qn, 2Qn 3Qn 4Qn 1Q, 2Q [6] FREF K x FREF M x FREF Output Frequency 3Q (1/K) x FREF FREF (M/K) x FREF 4Q (1/M) x FREF (K/M) x FREF FREF
4
PE
I, PU I I O PWR PWR PWR PWR PWR
LVTTL
24, 23, 26, 25, 1, 32, 3, 2 31 19, 20, 15, 16,10,11, 6, 7 21 12 5 14,30 8, 9, 17, 18, 28
nF[1:0] FS nQ[1:0] VDDQ1[2] VDDQ3[2] VDDQ4[2] VDD[2] VSS
3-Level 3-Level LVTTL
Power Power Power Power Power
Device Configuration
The outputs of the CY2V9950 can be configured to run at frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 1 and 2 respectively. Table 1. Output Divider Settings - Bank 3 3F[1:0] LL[4] HH Other K - Bank3 Output Divider 2 4 1
Table 2. Output Divider Settings - Bank 4 4F[1:0] LL[4] HH Other M - Bank4 Output Divider 2 Inverted[5] 1
The 3-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY2V9950 PLL operating frequency range that corresponds to each FS level is given in Table 4.
Notes: 1. `PD' indicates an internal pull-down and `PU' indicates an internal pull-up. `3' indicates a three-level input buffer. 2. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. The 1F[0:1] and 2F[0:1] pins should be either tied to mid-level or left floating (on-chip resistors will bias to mid-level) during normal operation. 4. LL disables outputs if TEST = MID and sOE# = HIGH. 5. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH, sOE# disables them LOW when PE = LOW. 6. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency at a given reference frequency (FREF) and divider and feedback configurations. The user must select a configuration and a reference frequency that will generate a VCO frequency that is within the range specified by FS pin. Refer to Table 4.
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CY2V9950
Table 4. Frequency Range Select FS L M H PLL Frequency Range 24 to 50 MHz 48 to 100 MHz 96 to 200 MHz Table 6. Power Supply Constraints VDD 3.3V 2.5V VDDQ1[7] 3.3V or 2.5V 2.5V VDDQ3[7] 3.3V or 2.5V 2.5V VDDQ4[7] 3.3V or 2.5V 2.5V
Governing Agencies
The following agencies provide specifications that apply to the CY2V9950. The agency name and relevant specification is listed below. Agency Name JEDEC IEEE UL-194_V0 MIL Specification JESD 51 (Theta JA) JESD 65 (Skew, Jitter) 1596.3 (Jiter Specs) 94 (Moisture Grading) 883E Method 1012.1 (Therma Theta JC)
The PE pin determines whether the outputs synchronize to the rising edge or the falling edge of the reference signal, as indicated in Table 5. Table 5. PE Settings PE L H Synchronization Negative Positive
The CY2V9950 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level which is equal or higher than that on any one of the output power supplies.
Absolute Maximum Conditions
Parameter VDD VDD VIN(MIN) VIN(MAX) TS TA TJ ESDHBM OJC OJA UL-94 MSL FIT Parameter VDD VIL VIH VIHH[8] VIMM[8] VILL[8] IIL Description Operating Voltage Operating Voltage Input Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Failure in Time Manufacturing Testing Condition Functional @ 2.5V 5% Functional @ 3.3V 10% Relative to VSS Relative to VDD Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) @1/8 in. Min. 2.25 2.97 VSS - 0.3 - -65 -40 - 2000 42 105 V-0 1 10 ppm Max. 2.75 3.63 - VDD + 0.3 +150 +85 155 - Unit V V V V C C C V C/W C/W
DC Electrical Specifications @ 2.5V
Description 2.5 Operating Voltage Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current 3-Level Inputs (TEST, FS, nF[1:0]) (These pins are normally wired to VDD,GND or unconnected) VIN = VDD/GND,VDD = Max (REF, PE, and FB inputs) 2.5V 5% REF, FB, PE, and sOE# Inputs Conditions Min. 2.375 - 1.7 VDD - -0.4 VDD/2-0.2 - -5 Max. 2.625 0.7 - - VDD/2 + 0.2 0.4 5 Unit V V V V V V A
Notes: 7. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g., VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V and VDDQ4 = 2.5V. 8. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
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CY2V9950
DC Electrical Specifications @ 2.5V (continued)
I3 3-Level Input DC Current HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS IPU IPD VOL VOH IDDQ IDD CIN Input Pull-up Current Input Pull-down Current Output LOW Voltage Output HIGH Voltage Quiescent Supply Current VIN = VSS, VDD = Max VIN = VDD, VDD = Max, (sOE#) IOL = 12 mA (nQ[0:1]) IOH = -12 mA (nQ[0:1]) VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded @100 MHz 3-Level Inputs (TEST, FS, nF[1:0]) - -50 -200 -25 - - 2.0 - 150 4 200 50 - - 100 0.4 - 2 A A A A A V V mA mA pF
Dynamic Supply Current Input Pin Capacitance
DC Electrical Specifications @ 3.3V
Parameter VDD VIL VIH VIHH[8] VIMM[8] VILL[8] IIL I3 Description 3.3 Operating Voltage Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current 3-Level Input DC Current 3-Level Inputs (TEST, FS, nF[1:0]) (These pins are normally wired to VDD,GND or unconected) VIN = VDD/GND,VDD = Max (REF, PE, and FB inputs) HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS IPU IPD VOL VOH IDDQ IDD CIN Input Pull-Up Current Input Pull-Down Current Output LOW Voltage Output HIGH Voltage Quiescent Supply Current VIN = VSS, VDD = Max VIN = VDD, VDD = Max, (sOE#) IOL = 12 mA, (nQ[0:1]) IOH = -12 mA, (nQ[0:1]) VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, outputs not loaded @100 MHz 3-Level Inputs (TEST, FS, nF[1:0]) 3.3V 10% REF, FB, PE, and sOE# Inputs Condition Min. 2.97 - 2.0 VDD - -0.6 VDD/2 - 0.3 - -5 - -50 -200 -100 - - 2.4 - 230 4 Max. 3.63 0.8 - - VDD/2 + 0.3 0.6 5 200 50 - - 100 0.4 - 2 Unit V V V V V V A A A A A A V V mA mA pF
Dynamic Supply Current Input Pin Capacitance
AC Input Specifications
Parameter TR,TF TPWC TDCIN FREF Description Input Rise/Fall Time Input Clock Pulse Input Duty Cycle Reference Input Frequency FS = LOW FS = MID FS = HIGH 0.8V - 2.0V HIGH or LOW Condition Min. - 2 10 6 12 24 Max. 10 - 90 50 100 200 MHz Unit ns/V ns %
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CY2V9950
Switching Characteristics
Parameter FOR VCOLR VCOLBW tSKEWPR tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tSKEW5 tPART tPD0 tODCV tPWH tPWL tR/tF tLOCK tCCJ Part-Part Skew Ref to FB Propagation Delay[10] Output Duty Cycle Output High Time Deviation from 50% Output Low Time Deviation from 50% Output Rise/Fall Time PLL lock time[11,12] Cycle-Cycle Jitter Divide by 1 output frequency, FS = L, FB = divide by 1, 2, 4 Divide by 1 output frequency, FS = M/H, FB = divide by 1, 2, 4 Measured at VDD/2 Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. Measured at 0.8V - 2.0V for VDD = 3.3V and 0.7V - 1.7V for VDD = 2.5V Description Output frequency range VCO Lock Range VCO Loop Bandwidth Matched-Pair Skew[9] Skew between the earliest and the latest output transitions within the same bank Skew between the earliest and the latest output transitions among all outputs Skew between the earliest and the latest output transitions among all same class outputs Skew between the nominal output rising edge to the inverted output falling edge Skew between non-inverted outputs running at different frequencies Skew between nominal to inverted outputs running at different frequencies Skew between nominal outputs at different power supply levels Skew between the outputs of any two devices under identical settings and conditions (VDDQ, VDD, temp, air flow, frequency, etc.) Condition Min. 6 200 0.25 - - - - - - - - -250 45 - - 0.15 - - - Max. 200 400 3.5 150 200 200 500 500 500 650 750 +250 55 1.5 2.0 1.5 0.5 100 150 Unit MHz MHz MHz ps ps ps ps ps ps ps ps ps % ns ns ns ms ps ps
Output-Output Skew[9]
Notes: 9. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded. 10. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5ns between 0.8V-2.0V. 11. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 12. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter.
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CY2V9950
AC Timing Definitions
tREF tPWH tPWL
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR tSKEW0,1
tSKEWPR tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
REF DIVIDED BY 2
tSKEW1,3,4
tSKEW1,3,4
REF DIVIDED BY 4
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CY2V9950
AC Test Loads and Waveforms
VDDQ
Output 20pF Output
150
150
20pF
For Lock Output
Figure 1.
tORISE tOFALL
For All Other Outputs
tORISE tOFALL
2.0V VTH =1.5V 0.8V tPWL
tPWH
1.7V VTH =1.25V 0.7V
tPWH
tPWL
2.5V LVTTL OUTPUT WAVEFORM 3.3V LVTTL OUTPUT WAVEFORM Figure 2. LVTTL Output Test Waveforms
1ns
3.0V 2.0V VTH =1.5V 0.8V 0V
1ns
2.5V 1.7V VTH =1.25V 0.7V 0V
1ns
1ns
3.3V LVTTL INPUT TEST WAVEFORM
2.5V LVTTL INPUT TEST WAVEFORM
Figure 3. LVTTL Input Test Waveforms
Ordering Information
Part Number CY2V9950AC CY2V9950ACT CY2V9950AI CY2V9950AIT 32 TQFP 32 TQFP - Tape and Reel 32 TQFP 32 TQFP - Tape and Reel Package Type Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C
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CY2V9950
Package Drawing and Dimensions
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-B
All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY2V9950
Document History Page
Document Title:CY2V9950 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer Document Number: 38-07436 REV. ** *A ECN No. 122628 252355 Issue Date 01/10/03 See ECN Orig. of Change RGL RGL/GGK New Data Sheet Fixed Note 3 definition. Description of Change
Document #: 38-07436 Rev. *A
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